Abstract
Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.
Original language | English |
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Title of host publication | IEEE International Reliability Physics Symposium Proceedings |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | SE41-SE45 |
Volume | 2016-September |
ISBN (Print) | 9781467391368 |
DOIs | |
Publication status | Published - 22 Sept 2016 |
Event | 2016 International Reliability Physics Symposium, IRPS 2016 - Pasadena, United States Duration: 17 Apr 2016 → 21 Apr 2016 |
Conference
Conference | 2016 International Reliability Physics Symposium, IRPS 2016 |
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Country/Territory | United States |
City | Pasadena |
Period | 17/04/16 → 21/04/16 |