Exploiting low power circuit topologies for soft error mitigation

N. N. Mahatme; I. Chatterjee; S. Jagannathan; N. Gaspard; T. Assis; S. J. Wen; R. Wong; B. L. Bhuva

doi:10.1109/IRPS.2016.7574640

Exploiting low power circuit topologies for soft error mitigation

N. N. Mahatme, I. Chatterjee, S. Jagannathan, N. Gaspard, T. Assis, S. J. Wen, R. Wong, B. L. Bhuva

School of Physics

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

Original language	English
Title of host publication	IEEE International Reliability Physics Symposium Proceedings
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	SE41-SE45
Volume	2016-September
ISBN (Print)	9781467391368
DOIs	https://doi.org/10.1109/IRPS.2016.7574640
Publication status	Published - 22 Sept 2016
Event	2016 International Reliability Physics Symposium, IRPS 2016 - Pasadena, United States Duration: 17 Apr 2016 → 21 Apr 2016

Conference

Conference	2016 International Reliability Physics Symposium, IRPS 2016
Country/Territory	United States
City	Pasadena
Period	17/04/16 → 21/04/16

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Mahatme, N. N., Chatterjee, I., Jagannathan, S., Gaspard, N., Assis, T., Wen, S. J., Wong, R., & Bhuva, B. L. (2016). Exploiting low power circuit topologies for soft error mitigation. In IEEE International Reliability Physics Symposium Proceedings (Vol. 2016-September, pp. SE41-SE45). Article 7574640 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/IRPS.2016.7574640

@inproceedings{7bd06c510236420397e3126295a1deaf,

title = "Exploiting low power circuit topologies for soft error mitigation",

abstract = "Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.",

author = "Mahatme, {N. N.} and I. Chatterjee and S. Jagannathan and N. Gaspard and T. Assis and Wen, {S. J.} and R. Wong and Bhuva, {B. L.}",

year = "2016",

month = sep,

day = "22",

doi = "10.1109/IRPS.2016.7574640",

language = "English",

isbn = "9781467391368",

volume = "2016-September",

pages = "SE41--SE45",

booktitle = "IEEE International Reliability Physics Symposium Proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2016 International Reliability Physics Symposium, IRPS 2016 ; Conference date: 17-04-2016 Through 21-04-2016",

}

Mahatme, NN, Chatterjee, I, Jagannathan, S, Gaspard, N, Assis, T, Wen, SJ, Wong, R & Bhuva, BL 2016, Exploiting low power circuit topologies for soft error mitigation. in IEEE International Reliability Physics Symposium Proceedings. vol. 2016-September, 7574640, Institute of Electrical and Electronics Engineers (IEEE), pp. SE41-SE45, 2016 International Reliability Physics Symposium, IRPS 2016, Pasadena, United States, 17/04/16. https://doi.org/10.1109/IRPS.2016.7574640

Exploiting low power circuit topologies for soft error mitigation. / Mahatme, N. N.; Chatterjee, I.; Jagannathan, S. et al.
IEEE International Reliability Physics Symposium Proceedings. Vol. 2016-September Institute of Electrical and Electronics Engineers (IEEE), 2016. p. SE41-SE45 7574640.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Exploiting low power circuit topologies for soft error mitigation

AU - Mahatme, N. N.

AU - Chatterjee, I.

AU - Jagannathan, S.

AU - Gaspard, N.

AU - Assis, T.

AU - Wen, S. J.

AU - Wong, R.

AU - Bhuva, B. L.

PY - 2016/9/22

Y1 - 2016/9/22

N2 - Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

AB - Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

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DO - 10.1109/IRPS.2016.7574640

M3 - Conference Contribution (Conference Proceeding)

AN - SCOPUS:84990988113

SN - 9781467391368

VL - 2016-September

SP - SE41-SE45

BT - IEEE International Reliability Physics Symposium Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 2016 International Reliability Physics Symposium, IRPS 2016

Y2 - 17 April 2016 through 21 April 2016

ER -

Exploiting low power circuit topologies for soft error mitigation

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