Exploiting low power circuit topologies for soft error mitigation

N. N. Mahatme, I. Chatterjee, S. Jagannathan, N. Gaspard, T. Assis, S. J. Wen, R. Wong, B. L. Bhuva

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

Original languageEnglish
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
PagesSE41-SE45
Volume2016-September
ISBN (Print)9781467391368
DOIs
Publication statusPublished - 22 Sep 2016
Event2016 International Reliability Physics Symposium, IRPS 2016 - Pasadena, United States
Duration: 17 Apr 201621 Apr 2016

Conference

Conference2016 International Reliability Physics Symposium, IRPS 2016
CountryUnited States
CityPasadena
Period17/04/1621/04/16

Fingerprint Dive into the research topics of 'Exploiting low power circuit topologies for soft error mitigation'. Together they form a unique fingerprint.

Cite this