Exploration of Through-Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Original language	Undefined/Unknown
Title of host publication	Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)
Publication status	Published - 1 Apr 2009

Research Groups and Themes

@inproceedings{1bea2994db1c4f538655834e08daaea3,

title = "Exploration of Through-Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits",

author = "Matt Grange and Roshan Weerasekera and Dinesh Pamunuwa and Hannu Tenhunen",

year = "2009",

month = apr,

day = "1",

language = "Undefined/Unknown",

booktitle = "Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)",

}

Exploration of Through-Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits. / Grange, Matt; Weerasekera, Roshan; Pamunuwa, Dinesh et al.
Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE). 2009.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Exploration of Through-Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

AU - Grange, Matt

AU - Weerasekera, Roshan

AU - Pamunuwa, Dinesh

AU - Tenhunen, Hannu

PY - 2009/4/1

Y1 - 2009/4/1

M3 - Conference Contribution (Conference Proceeding)

BT - Proc. Special Interest Workshop on 3D Integration -- Design Automation and Test in Europe (DATE)

ER -