Exploring dynamically reconfigurable multicore designs with NoRC designer

Jose Nunez-Yanez, Arash Farhadi Beldachi, Atukem Nabina, Mohammad Hosseinabady

Research output: Contribution to conferenceConference Paperpeer-review

Abstract

This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes in application requirements, operating conditions and/or process variations. The NoRC system is oriented at avoiding any centralized control with functions mapped to tiles at runtime depending on processing capabilities and location. The dynamic nature of the platform means that following a request for an application from an external host any idle tile can be configured as a master able to make additional requests to nearby tiles or as a slave able to service the requests. NoRC designer is used in this paper to investigate possible task mapping strategies suitable for this type of adaptive platform and also the power and partial reconfiguration overheads of commercial FPGAs.
Original languageEnglish
DOIs
Publication statusPublished - 2012
EventThe 2012 International Conference on High Performance Computing & Simulation (HPCS 2012) - Madrid, Madrid, Spain
Duration: 2 Jun 20126 Jun 2012
http://hpcs2012.cisedu.info/

Conference

ConferenceThe 2012 International Conference on High Performance Computing & Simulation (HPCS 2012)
CountrySpain
CityMadrid
Period2/06/126/06/12
Internet address

Fingerprint Dive into the research topics of 'Exploring dynamically reconfigurable multicore designs with NoRC designer'. Together they form a unique fingerprint.

Cite this