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eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip

Research output: Contribution to journalArticle

Original languageEnglish
Pages (from-to)148-162
Number of pages15
JournalIET Computers and Digital Techniques
Volume8
Issue number3
DOIs
DatePublished - May 2014

Abstract

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.

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  • XTRANC_modified_arash

    Rights statement: This paper is a postprint of a paper submitted to and accepted for publication in IET Computers & Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.

    Accepted author manuscript, 3.6 MB, Word document

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