Abstract
Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.
| Original language | Undefined/Unknown |
|---|---|
| Title of host publication | Proc. IEEE/ACM International Conference on Computer-Aided Design |
| Pages | 212-219 |
| Number of pages | 8 |
| DOIs | |
| Publication status | Published - 1 Nov 2007 |
Research Groups and Themes
- Photonics and Quantum
Keywords
- semiconductor device manufacture
- system-on-chip
- 2D planar SoC single-chip solutions
- cost trade-off analysis
- design cycle time
- electronic system design technology
- high-density portable hand-held applications
- single-level embedded modules
- system conceptual level
- systems-on-chip
- tiled silicon
- Circuit noise
- Cost function
- Dielectric substrates
- Fabrication
- Integrated circuit interconnections
- Performance analysis
- Power system interconnection
- Radio frequency
- Routing
- Silicon