Abstract
This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.
| Original language | English |
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| Title of host publication | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems |
| Pages | 107-111 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 1 Dec 2013 |
| Event | 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013 - New York City, NY, United Kingdom Duration: 2 Oct 2013 → 4 Oct 2013 |
Conference
| Conference | 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013 |
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| Country/Territory | United Kingdom |
| City | New York City, NY |
| Period | 2/10/13 → 4/10/13 |
Keywords
- Flip flop
- Multiple node upset
- radiation