Fast 2D-DCT implementations for VLIW processors

OP Sohm; CN Canagarajah; DR Bull

doi:10.1109/MMSP.1999.793940

Fast 2D-DCT implementations for VLIW processors

OP Sohm, CN Canagarajah, DR Bull

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

6 Citations (Scopus)

513 Downloads (Pure)

Abstract

This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure

Translated title of the contribution	Fast 2D-DCT implementations for VLIW processors
Original language	English
Title of host publication	IEEE Multimedia Signal Processing Workshop
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	655 - 660
ISBN (Print)	0780356101
DOIs	https://doi.org/10.1109/MMSP.1999.793940
Publication status	Published - Sept 1999
Event	3rd IEEE Workshop on Multimedia Signal Processing - Copenhagen, Denmark Duration: 1 Sept 1999 → …

Conference

Conference	3rd IEEE Workshop on Multimedia Signal Processing
Country/Territory	Denmark
City	Copenhagen
Period	1/09/99 → …

Bibliographical note

Rose publication type: Conference contribution

Terms of use: Copyright © 1999 IEEE. Reprinted from IEEE 3rd Workshop on Multimedia Signal Processing, 1999.

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

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Sohm IEEE multimedia 1999Accepted author manuscript, 247 KB

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title = "Fast 2D-DCT implementations for VLIW processors",

abstract = "This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure",

author = "OP Sohm and CN Canagarajah and DR Bull",

note = "Rose publication type: Conference contribution Terms of use: Copyright {\textcopyright} 1999 IEEE. Reprinted from IEEE 3rd Workshop on Multimedia Signal Processing, 1999. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; 3rd IEEE Workshop on Multimedia Signal Processing ; Conference date: 01-09-1999",

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AU - Canagarajah, CN

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PY - 1999/9

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N2 - This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure

AB - This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure

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DO - 10.1109/MMSP.1999.793940

M3 - Conference Contribution (Conference Proceeding)

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BT - IEEE Multimedia Signal Processing Workshop

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 3rd IEEE Workshop on Multimedia Signal Processing

Y2 - 1 September 1999

ER -

Fast 2D-DCT implementations for VLIW processors

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