This paper proposes a Network-on-Chip (NoC)-based dynamically reconfigurable platform which can perform multiple applications, simultaneously. A tile attached to a router in the NoC consists of a core container which can host a core permanently or temporarily. The tile also has a hardwired controller and a cache like memory to control the hosted cores. A core, which runs a task, may be described by a bitstream (called hardware core) or a programme code (called software core). Because of the dynamic behaviour of the proposed platform, using task identifier, a stochastic dynamic routing algorithm will find (or map) the task in the platform. Because of using the task identifier in routing algorithm and the reconfigurability of tiles, the proposed platform can tolerate probable faults. The proposed SoC architecture is easily able to run new protocols and tasks. Our results show that, the proposed platform follows the user interests such that runs tasks with higher temporal locality much faster than the tasks with lower temporal locality.
|Translated title of the contribution||Fault-tolerant dynamically reconfigurable NoC-based SoC|
|Title of host publication||International Conference on Application-Specific Systems, Architectures and Processors (ASAP2008), Leuven, Belgium|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||31 - 36|
|Number of pages||6|
|Publication status||Published - 2 Jul 2008|