Reliability is an emerging design requirement for finite field processors used in cryptographic systems. However, reliable design of these systems is particularly challenging due to conflicting design requirements, including high performance and low power consumption. In this paper, we propose a novel design technique for reliable and low power Galois field (OF) arithmetic processor. The aim is to tolerate faults in the OF processor during on-line computation at reduced system costs, while maintaining high performance. The reduction in system costs is achieved through multiple parity prediction and comparison considering the trade-offs between performance and complexity. The effectiveness of the proposed technique is then validated using a case study of 163-bit digit serial multipliers using 90nm and 180nm technology nodes highlighting the resulting area, latency and power overheads. We show that up to 40 stuck-at faults can be tolerated during computation with reasonable system area and power costs.