Abstract
The pseudo resistor (PR) is widely used in integrated circuits. It comprises two transistors back‐to‐back to force them into the sub‐threshold region, which provides large resistance with a small die area. However, its linearity is limited by the non‐linear MOS transistors in weak inversion. In this Letter, a new PR topology is proposed, employing a feedback loop that continuously adjusts the voltage at the shared gate node of the PR with the input signal. The proposed architecture substantially increases the linearity and impedance of the PR.
| Original language | English |
|---|---|
| Pages (from-to) | 371-373 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 56 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 1 Apr 2020 |
Bibliographical note
Publisher Copyright:© The Institution of Engineering and Technology 2020.