Field Plate Designs in All-GaN Cascode Heterojunction Field-Effect Transistors

Sheng Jiang*, Kean Boon Lee, Zaffar H. Zaidi, Michael J. Uren, Martin Kuball, Peter A. Houston

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)peer-review

1 Citation (Scopus)
200 Downloads (Pure)

Abstract

Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minimized capacitive energy loss and reduced overvoltage stress at the internode. This is attributed to the reduced ratio of the drain-source capacitance of the depletion mode cascode part to the total capacitance at the cascode internode. An additional FP on the E-mode cascode part is proposed to further suppress the off-state internode voltage and benefit the device. Cascode devices with the source FP connecting to the enhancement mode gate have an improved switching controllability via gate resistance during turn-off and hence enhanced dv/dt immunity in the drain loop.

Original languageEnglish
Article number8648532
Pages (from-to)1688-1693
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume66
Issue number4
Early online date21 Feb 2019
DOIs
Publication statusPublished - 1 Apr 2019

Keywords

  • Power electronics
  • semiconductor devices
  • semiconductor heterojunctions
  • semiconductor switches

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