This paper presents a Design-for-Veriﬁcation approach applied to verify critical properties of a complex, programmable, performance-critical processor communication interface. The functional and performance requirements have been systematically decomposed into functionally independent communicating building blocks that can be individually veriﬁed and that when composed together exhibit the properties required to run a speciﬁc communication protocol.
|Translated title of the contribution||Formal Analysis of a Programmable Performance-Critical Processor Communication Interface|
|Title of host publication||Proceedings of the 10th International Workshop on Automated Veriﬁcation of Critical Systems (AVoCS 2010)|
|Publication status||Published - 2010|
Bibliographical noteOther page information: tbc-
Conference Proceedings/Title of Journal: Proceedings of the 10th International Workshop on Automated Veriﬁcation of Critical Systems (AVoCS 2010)
Other identifier: 2001286