Abstract
This paper presents a Design-for-Verification approach applied to verify critical properties of a complex, programmable, performance-critical processor communication interface. The functional and performance requirements have been systematically decomposed into functionally independent communicating building blocks that can be individually verified and that when composed together exhibit the
properties required to run a specific communication protocol.
Translated title of the contribution | Formal Analysis of a Programmable Performance-Critical Processor Communication Interface |
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Original language | English |
Title of host publication | Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (AVoCS 2010) |
Publisher | tbc |
Publication status | Published - 2010 |
Bibliographical note
Other page information: tbc-Conference Proceedings/Title of Journal: Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (AVoCS 2010)
Other identifier: 2001286