Formal Analysis of a Programmable Performance-Critical Processor Communication Interface

S Abu Kharmeh, Kerstin Eder, David May

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

This paper presents a Design-for-Verification approach applied to verify critical properties of a complex, programmable, performance-critical processor communication interface. The functional and performance requirements have been systematically decomposed into functionally independent communicating building blocks that can be individually verified and that when composed together exhibit the properties required to run a specific communication protocol.
Translated title of the contributionFormal Analysis of a Programmable Performance-Critical Processor Communication Interface
Original languageEnglish
Title of host publicationProceedings of the 10th International Workshop on Automated Verification of Critical Systems (AVoCS 2010)
Publishertbc
Publication statusPublished - 2010

Bibliographical note

Other page information: tbc-
Conference Proceedings/Title of Journal: Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (AVoCS 2010)
Other identifier: 2001286

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