FPGA-based modelling unit for high speed lossless arithmetic coding

R Stefo, JL Nunez-Yanez, C Feregrino, S Mahapatra, S Jones

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

10 Citations (Scopus)

Translated title of the contribution	FPGA-based modelling unit for high speed lossless arithmetic coding
Original language	English
Title of host publication	11th International Conference on Field Programmable Logic and Applications (FPL'2001), Belfast, N Ireland
Publication status	Published - 27 Aug 2001

Conference Proceedings/Title of Journal: 11th International Conference on Field Programmable Logic and Applications (FPL'2001)

Handle.net

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title = "FPGA-based modelling unit for high speed lossless arithmetic coding",

author = "R Stefo and JL Nunez-Yanez and C Feregrino and S Mahapatra and S Jones",

note = "Conference Proceedings/Title of Journal: 11th International Conference on Field Programmable Logic and Applications (FPL'2001)",

year = "2001",

month = aug,

day = "27",

language = "English",

booktitle = "11th International Conference on Field Programmable Logic and Applications (FPL'2001), Belfast, N Ireland",

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TY - GEN

T1 - FPGA-based modelling unit for high speed lossless arithmetic coding

AU - Stefo, R

AU - Nunez-Yanez, JL

AU - Feregrino, C

AU - Mahapatra, S

AU - Jones, S

N1 - Conference Proceedings/Title of Journal: 11th International Conference on Field Programmable Logic and Applications (FPL'2001)

PY - 2001/8/27

Y1 - 2001/8/27

M3 - Conference Contribution (Conference Proceeding)

BT - 11th International Conference on Field Programmable Logic and Applications (FPL'2001), Belfast, N Ireland

ER -