Fully pipelined bloom filter architecture

M Paynter, T Koçak

Research output: Contribution to journalArticle (Academic Journal)peer-review

14 Citations (Scopus)
359 Downloads (Pure)

Abstract

Recently, we proposed a two-stage pipelined Bloom filter architecture to save power for network security applications. In this letter, we generalize the pipelined Bloom filter architecture to k-stage and show that significant power savings can be achieved by employing one hash function per stage. We analytically show that the expected power consumption and latency of the fully pipelined Bloom filter architecture will not be greater than that of the two hash functions and two clock cycles, respectively, however large the number of hash functions is. Furthermore, we discuss the worst-case performance of the proposed architecture
Translated title of the contributionFully pipelined bloom filter architecture
Original languageEnglish
Pages (from-to)855 - 857
Number of pages3
JournalIEEE Communications Letters
Volume12
Issue number11
DOIs
Publication statusPublished - Nov 2008

Bibliographical note

Publisher: IEEE
Rose publication type: Journal article

Terms of use: Copyright © 2008 IEEE. Reprinted from IEEE Communications Letters.

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Keywords

  • bloom filters
  • network intrusion detection
  • low-power design

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