Abstract
Recently, we proposed a two-stage pipelined Bloom filter architecture to save power for network security applications. In this letter, we generalize the pipelined Bloom filter architecture to k-stage and show that significant power savings can be achieved by employing one hash function per stage. We analytically show that the expected power consumption and latency of the fully pipelined Bloom filter architecture will not be greater than that of the two hash functions and two clock cycles, respectively, however large the number of hash functions is. Furthermore, we discuss the worst-case performance of the proposed architecture
| Translated title of the contribution | Fully pipelined bloom filter architecture |
|---|---|
| Original language | English |
| Pages (from-to) | 855 - 857 |
| Number of pages | 3 |
| Journal | IEEE Communications Letters |
| Volume | 12 |
| Issue number | 11 |
| DOIs | |
| Publication status | Published - Nov 2008 |
Bibliographical note
Publisher: IEEERose publication type: Journal article
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Keywords
- bloom filters
- network intrusion detection
- low-power design