Gate level optimisation of primitive operator digital filters using a carry save decomposition

DR Bull; G Wacey

doi:10.1109/ISCAS.1994.408913

Gate level optimisation of primitive operator digital filters using a carry save decomposition

DR Bull
, G Wacey

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

1 Citation (Scopus)

478 Downloads (Pure)

Abstract

This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a carry-save decomposition of the primitive operator graph. This facilitates the generation of a set of Boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20% for the Reed Muller case

Translated title of the contribution	Gate level optimisation of primitive operator digital filters using a carry save decomposition
Original language	English
Title of host publication	Unknown
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	93 - 96
Number of pages	3
Volume	2
ISBN (Print)	078031915X
DOIs	https://doi.org/10.1109/ISCAS.1994.408913
Publication status	Published - May 1994
Event	International Symposium on Circuits and Systems - London, United Kingdom Duration: 1 May 1994 → …

Conference

Conference	International Symposium on Circuits and Systems
Country/Territory	United Kingdom
City	London
Period	1/05/94 → …

Bibliographical note

Conference Proceedings/Title of Journal: Proc. 1994 IEEE Int. Sym. on Circuits and Systems
Rose publication type: Conference contribution

Sponsorship: The authors would like to express their thanks to Nigel Lester of the Department of Electrical and Electronic Engineering at
the University of Bristol for his assistance in producing the logic minimisation results presented here

Terms of use: Copyright © 1994 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1994 (ISCAS '94).

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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10.1109/ISCAS.1994.408913

Bull2 IEEE ISCAS 1994Accepted author manuscript, 299 KB

http://hdl.handle.net/1983/1513

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title = "Gate level optimisation of primitive operator digital filters using a carry save decomposition",

abstract = "This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a carry-save decomposition of the primitive operator graph. This facilitates the generation of a set of Boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83\% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20\% for the Reed Muller case",

author = "DR Bull and G Wacey",

note = "Conference Proceedings/Title of Journal: Proc. 1994 IEEE Int. Sym. on Circuits and Systems Rose publication type: Conference contribution Sponsorship: The authors would like to express their thanks to Nigel Lester of the Department of Electrical and Electronic Engineering at the University of Bristol for his assistance in producing the logic minimisation results presented here Terms of use: Copyright {\textcopyright} 1994 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1994 (ISCAS '94). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; International Symposium on Circuits and Systems ; Conference date: 01-05-1994",

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TY - GEN

T1 - Gate level optimisation of primitive operator digital filters using a carry save decomposition

AU - Bull, DR

AU - Wacey, G

N1 - Conference Proceedings/Title of Journal: Proc. 1994 IEEE Int. Sym. on Circuits and Systems Rose publication type: Conference contribution Sponsorship: The authors would like to express their thanks to Nigel Lester of the Department of Electrical and Electronic Engineering at the University of Bristol for his assistance in producing the logic minimisation results presented here Terms of use: Copyright © 1994 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 1994 (ISCAS '94). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

PY - 1994/5

Y1 - 1994/5

N2 - This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a carry-save decomposition of the primitive operator graph. This facilitates the generation of a set of Boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20% for the Reed Muller case

AB - This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a carry-save decomposition of the primitive operator graph. This facilitates the generation of a set of Boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20% for the Reed Muller case

U2 - 10.1109/ISCAS.1994.408913

DO - 10.1109/ISCAS.1994.408913

M3 - Conference Contribution (Conference Proceeding)

SN - 078031915X

VL - 2

SP - 93

EP - 96

BT - Unknown

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - International Symposium on Circuits and Systems

Y2 - 1 May 1994

ER -

Gate level optimisation of primitive operator digital filters using a carry save decomposition

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