Gbit/s lossless data compression hardware

Research output: Contribution to journalArticle (Academic Journal)peer-review

56 Citations (Scopus)


This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.
Translated title of the contributionGbit/s lossless data compression hardware
Original languageEnglish
Article numberIssue 3
Pages (from-to)499 - 510
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication statusPublished - Jun 2003

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

Fingerprint Dive into the research topics of 'Gbit/s lossless data compression hardware'. Together they form a unique fingerprint.

Cite this