Abstract
This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.
| Translated title of the contribution | Gbit/s lossless data compression hardware |
|---|---|
| Original language | English |
| Article number | Issue 3 |
| Pages (from-to) | 499 - 510 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 11 |
| DOIs | |
| Publication status | Published - Jun 2003 |
Bibliographical note
Publisher: Institute of Electrical and Electronics Engineers (IEEE)Fingerprint
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