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Hardware acceleration of the Tate pairing in characteristic three

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

Hardware acceleration of the Tate pairing in characteristic three. / Grabher, P; Page, Daniel.

Cryptographic Hardware and Embedded Systems - CHES 2005. Vol. 3659 Springer Berlin Heidelberg, 2005. p. 398-411.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Grabher, P & Page, D 2005, Hardware acceleration of the Tate pairing in characteristic three. in Cryptographic Hardware and Embedded Systems - CHES 2005. vol. 3659, Springer Berlin Heidelberg, pp. 398-411.

APA

Grabher, P., & Page, D. (2005). Hardware acceleration of the Tate pairing in characteristic three. In Cryptographic Hardware and Embedded Systems - CHES 2005 (Vol. 3659, pp. 398-411). Springer Berlin Heidelberg.

Vancouver

Grabher P, Page D. Hardware acceleration of the Tate pairing in characteristic three. In Cryptographic Hardware and Embedded Systems - CHES 2005. Vol. 3659. Springer Berlin Heidelberg. 2005. p. 398-411

Author

Grabher, P ; Page, Daniel. / Hardware acceleration of the Tate pairing in characteristic three. Cryptographic Hardware and Embedded Systems - CHES 2005. Vol. 3659 Springer Berlin Heidelberg, 2005. pp. 398-411

Bibtex

@inproceedings{0fcd504c1a3d4a9cb1577c38f2646320,
title = "Hardware acceleration of the Tate pairing in characteristic three",
abstract = "Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core computational task is evaluation of a bilinear map, or pairing, over elliptic curves. In this paper we prototype and evaluate polynomial and normal basis field arithmetic on an FPGA device and use it to construct a hardware accelerator for pairings over fields of characteristic three. The performance of our prototype improves roughly ten-fold on previous known hardware implementations and orders of magnitude on the fastest known software implementation. As a result we reason that even on constrained devices one can usefully evaluate the pairing, a fact that gives credence to the idea that identity based cryptography is an ideal partner for identity aware smart-cards.",
author = "P Grabher and Daniel Page",
year = "2005",
language = "English",
volume = "3659",
pages = "398--411",
booktitle = "Cryptographic Hardware and Embedded Systems - CHES 2005",
publisher = "Springer Berlin Heidelberg",
address = "Germany",

}

RIS - suitable for import to EndNote

TY - GEN

T1 - Hardware acceleration of the Tate pairing in characteristic three

AU - Grabher, P

AU - Page, Daniel

PY - 2005

Y1 - 2005

N2 - Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core computational task is evaluation of a bilinear map, or pairing, over elliptic curves. In this paper we prototype and evaluate polynomial and normal basis field arithmetic on an FPGA device and use it to construct a hardware accelerator for pairings over fields of characteristic three. The performance of our prototype improves roughly ten-fold on previous known hardware implementations and orders of magnitude on the fastest known software implementation. As a result we reason that even on constrained devices one can usefully evaluate the pairing, a fact that gives credence to the idea that identity based cryptography is an ideal partner for identity aware smart-cards.

AB - Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core computational task is evaluation of a bilinear map, or pairing, over elliptic curves. In this paper we prototype and evaluate polynomial and normal basis field arithmetic on an FPGA device and use it to construct a hardware accelerator for pairings over fields of characteristic three. The performance of our prototype improves roughly ten-fold on previous known hardware implementations and orders of magnitude on the fastest known software implementation. As a result we reason that even on constrained devices one can usefully evaluate the pairing, a fact that gives credence to the idea that identity based cryptography is an ideal partner for identity aware smart-cards.

M3 - Conference contribution

VL - 3659

SP - 398

EP - 411

BT - Cryptographic Hardware and Embedded Systems - CHES 2005

PB - Springer Berlin Heidelberg

ER -