Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding

X Chen, CN Canagarajah, JL Nunez-Yanez, Raffaele Vitulli

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)
253 Downloads (Pure)

Abstract

In this paper we present a novel hardware architecture for context-based statistical lossless image compression, as part of a dynamically reconfigurable architecture for universal lossless compression. A gradient-adjusted prediction and context modeling algorithm is adapted to a pipelined scheme for low complexity and high throughput. Our proposed system improves image compression ratio while keeping low hardware complexity. This system is designed for a Xilinx Virtex4 FPGA core and optimized to achieve a 123 MHz clock frequency for real-time processing.
Translated title of the contributionHardware architecture for lossless image compression based on context-based modeling and arithmetic coding
Original languageEnglish
Title of host publicationIEEE International SOC Conference, Hsin Chu, Taiwan
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages251 - 254
ISBN (Print)9781424415922
DOIs
Publication statusPublished - Sep 2007
EventIEEE International SOC Conference - Hsin Chu, Taiwan
Duration: 1 Sep 2007 → …

Conference

ConferenceIEEE International SOC Conference
CountryTaiwan
CityHsin Chu
Period1/09/07 → …

Bibliographical note

Conference Proceedings/Title of Journal: IEEE International SOC Conference, 2007
Rose publication type: Conference contribution

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