In this paper we present a novel hardware architecture for context-based statistical lossless image compression, as part of a dynamically reconfigurable architecture for universal lossless compression. A gradient-adjusted prediction and context modeling algorithm is adapted to a pipelined scheme for low complexity and high throughput. Our proposed system improves image compression ratio while keeping low hardware complexity. This system is designed for a Xilinx Virtex4 FPGA core and optimized to achieve a 123 MHz clock frequency for real-time processing.
|Translated title of the contribution||Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding|
|Title of host publication||IEEE International SOC Conference, Hsin Chu, Taiwan|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||251 - 254|
|Publication status||Published - Sep 2007|
|Event||IEEE International SOC Conference - Hsin Chu, Taiwan|
Duration: 1 Sep 2007 → …
|Conference||IEEE International SOC Conference|
|Period||1/09/07 → …|
Bibliographical noteConference Proceedings/Title of Journal: IEEE International SOC Conference, 2007
Rose publication type: Conference contribution
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