This paper investigates the algorithmic complexity of rate distortion optimization in the new H.264 video coding standard and proposes a hardware accelerator to reduce it by more than an order of magnitude. The accelerator incorporates an arithmetic coding engine and efficiently handles all the context information needed by RDO and CABAC in H.264. The bit stream generated by the CABAC engine is equivalent to that generated by the JM 9.4 reference software. The ISA of a controlling scalar RISC CPU has been extended with RDO/CABAC instructions and a implementation prototyped using state-of-the-art FPGA technology.
|Translated title of the contribution||Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec|
|Title of host publication||2006 Digest of Technical Papers International Conference on Consumer Electronics|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||2|
|Publication status||Published - 2006|
Bibliographical notePublisher: Institute of Electrical and Electronics Engineers Inc (IEEE)
Name and Venue of Conference: IEEE International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA