Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

JL Nunez-Yanez, VA Chouliaras, D Alfonso

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)

Abstract

This paper investigates the algorithmic complexity of rate distortion optimization in the new H.264 video coding standard and proposes a hardware accelerator to reduce it by more than an order of magnitude. The accelerator incorporates an arithmetic coding engine and efficiently handles all the context information needed by RDO and CABAC in H.264. The bit stream generated by the CABAC engine is equivalent to that generated by the JM 9.4 reference software. The ISA of a controlling scalar RISC CPU has been extended with RDO/CABAC instructions and a implementation prototyped using state-of-the-art FPGA technology.
Translated title of the contributionHardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec
Original languageEnglish
Title of host publication2006 Digest of Technical Papers International Conference on Consumer Electronics
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages95-96
Number of pages2
ISBN (Print)0780394593
DOIs
Publication statusPublished - 2006

Publication series

Name
ISSN (Print)2158-3994

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers Inc (IEEE)
Name and Venue of Conference: IEEE International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA

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