High-Fidelity Device Modelling of SiC MOSFETs for Active Gate Drive Optimisation

Active gate driving enables the shaping of switching waveforms in power devices, helping to mitigate overshoot and ringing. With the advent of smart, open-loop, programmable gate drivers, selecting gate control parameters is challenging, and testing these in hardware is time-consuming and potentially risky. This paper proposes a faster, safer simulation-based method for optimising gate current profiles, requiring high-fidelity device models. A commercial model is modified using measured device properties, specifically input capacitance, recovery charge, and high-voltage transfer behaviour, whilst experimental switching waveforms are reserved exclusively for validation, not model tuning. Gate profile optimisation begins with a measured gate current waveform, then modulates the current within a limited time window in simulation. Profiles are evaluated for overshoot, ringing and switching loss. The most promising are validated experimentally using a 1200 V, 17 A SiC MOSFET in an 800 V, 10 A half-bridge with a custom single-chip active gate driver capable of synthesising arbitrary current waveforms. To further assess robustness, power loop inductance is varied. The modified model shows good agreement with measurements, and the optimised gate profiles supress 180 MHz turn-on current ringing by 7 dB and reduce turn-off voltage overshoot by 20%, without increasing switching losses. This work demonstrates computationally efficient gate profile optimisation, with strong potential for application in smart gate drivers.