High-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V(CC)=0.5V) Logic Applications

M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jefferies, T. Martin, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith, MJ Uren, D. J. Wallis, P. J. Wilding, R. Chau

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

57 Citations (Scopus)

Abstract

This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230cm(2)/V-s. The shortest 40nm gate length (L(G)) transistors achieve peak transconductance (G(m)) of 510 mu S/mu m and cut-off frequency (f(T)) of 140GHz at supply voltage of 0.5V. These represent the highest G(m) and f(T) ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.
Translated title of the contributionHigh-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V(CC)=0.5V) Logic Applications
Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting
Pages727 - 730
Number of pages4
DOIs
Publication statusPublished - 2008

Fingerprint Dive into the research topics of 'High-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V(CC)=0.5V) Logic Applications'. Together they form a unique fingerprint.

Cite this