High-performance arithmetic coding VLSI macro for the H264 video compression standard

JL Nunez-Yanez, VA Chouliaras

Research output: Contribution to journalArticle (Academic Journal)peer-review

20 Citations (Scopus)
296 Downloads (Pure)

Abstract

This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.
Translated title of the contributionHigh-performance arithmetic coding VLSI macro for the H264 video compression standard
Original languageEnglish
Pages (from-to)144-151
Number of pages8
JournalIEEE Transactions on Consumer Electronics
Volume51
Issue number1
DOIs
Publication statusPublished - Feb 2005

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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