High-performance arithmetic coding VLSI macro for the H264 video compression standard

JL Nunez-Yanez; VA Chouliaras

doi:10.1109/TCE.2005.1405712

High-performance arithmetic coding VLSI macro for the H264 video compression standard

JL Nunez-Yanez, VA Chouliaras

Department of Electrical & Electronic Engineering

Research output: Contribution to journal › Article (Academic Journal) › peer-review

20 Citations (Scopus)

296 Downloads (Pure)

Abstract

This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.

Translated title of the contribution	High-performance arithmetic coding VLSI macro for the H264 video compression standard
Original language	English
Pages (from-to)	144-151
Number of pages	8
Journal	IEEE Transactions on Consumer Electronics
Volume	51
Issue number	1
DOIs	https://doi.org/10.1109/TCE.2005.1405712
Publication status	Published - Feb 2005

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

Access to Document

10.1109/TCE.2005.1405712

MacroSubmitted manuscript, 182 KB

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DO - 10.1109/TCE.2005.1405712

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