Abstract
This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.
Translated title of the contribution | High-performance arithmetic coding VLSI macro for the H264 video compression standard |
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Original language | English |
Pages (from-to) | 144-151 |
Number of pages | 8 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 51 |
Issue number | 1 |
DOIs | |
Publication status | Published - Feb 2005 |