High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

Kris Nikov; Mohammad Hosseinabady; Rafael Asenjo; Andrés Rodríguezz; Angeles Navarro; Jose Nunez-Yanez

doi:10.48550/arXiv.2008.08883

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguezz, Angeles Navarro, Jose Nunez-Yanez

Research output: Working paper

14 Downloads (Pure)

Abstract

This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.

Original language	English
Number of pages	8
DOIs	https://doi.org/10.48550/arXiv.2008.08883
Publication status	Unpublished - 20 Aug 2020

Bibliographical note

7 pages, 5 figures, 1 table Presented at the 13th International Workshop on Programmability and Architectures for Heterogeneous Multicores, 2020 (arXiv:2005.07619)

Keywords

FPGA
Xilinx ZCU102
Heterogeneous Scheduling
performance improvement

Access to Document

10.48550/arXiv.2008.08883

Full-text PDF (pre-print)
This is a pre-print server version of the article. It first appeared online via arXiv at https://arxiv.org/abs/2008.08883. Please refer to any applicable terms of use of the publisher
Submitted manuscript, 476 KBLicence: CC BY-NC-SA

Handle.net

Persistent link

Cite this

@techreport{b7e558dc11134d959f106f99101d9496,

title = "High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip",

abstract = "This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.",

keywords = "FPGA, Xilinx ZCU102, Heterogeneous Scheduling, performance improvement",

author = "Kris Nikov and Mohammad Hosseinabady and Rafael Asenjo and Andr{\'e}s Rodr{\'i}guezz and Angeles Navarro and Jose Nunez-Yanez",

note = "7 pages, 5 figures, 1 table Presented at the 13th International Workshop on Programmability and Architectures for Heterogeneous Multicores, 2020 (arXiv:2005.07619)",

year = "2020",

month = aug,

day = "20",

doi = "10.48550/arXiv.2008.08883",

language = "English",

type = "WorkingPaper",

}

TY - UNPB

T1 - High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

AU - Nikov, Kris

AU - Hosseinabady, Mohammad

AU - Asenjo, Rafael

AU - Rodríguezz, Andrés

AU - Navarro, Angeles

AU - Nunez-Yanez, Jose

N1 - 7 pages, 5 figures, 1 table Presented at the 13th International Workshop on Programmability and Architectures for Heterogeneous Multicores, 2020 (arXiv:2005.07619)

PY - 2020/8/20

Y1 - 2020/8/20

N2 - This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.

AB - This paper presents a methodology for simultaneous heterogeneous computing, named ENEAC, where a quad core ARM Cortex-A53 CPU works in tandem with a preprogrammed on-board FPGA accelerator. A heterogeneous scheduler distributes the tasks optimally among all the resources and all compute units run asynchronously, which allows for improved performance for irregular workloads. ENEAC achieves up to 17\% performance improvement \ignore{and 14\% energy usage reduction,} when using all platform resources compared to just using the FPGA accelerators and up to 865\% performance increase \ignore{and up to 89\% energy usage decrease} when using just the CPU. The workflow uses existing commercial tools and C/C++ as a single programming language for both accelerator design and CPU programming for improved productivity and ease of verification.

KW - FPGA

KW - Xilinx ZCU102

KW - Heterogeneous Scheduling

KW - performance improvement

U2 - 10.48550/arXiv.2008.08883

DO - 10.48550/arXiv.2008.08883

M3 - Working paper

BT - High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

ER -

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip

Abstract

Bibliographical note

Keywords

Access to Document

Handle.net

Fingerprint

Cite this