High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

C. Bolchini*, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaña, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

4 Citations (Scopus)

Abstract

While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits. In particular, the reduced integration step, the reduced supply voltage that lowers the noise immunity, the growing power needs, the eventual integration of both digital and analog circuits on the same chip and the highly growing of radiation sensitivity [1], [2], [3] require an accurate evaluation of possible reliability reduction for the occurrence of: permanent faults due to the aging of device materials [4], the interruptions of metal interconnections due to electromigration [5] or the crack of the insulation oxide of transistor [6]; transient faults, known as Single Event Effects (SEE), which are much more likely than in the past due to the reduced transistors' sizes [3]: in particular new technology devices are more prone to crosstalk in the interconnects and to radiation effects.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Pages121-125
Number of pages5
DOIs
Publication statusPublished - 1 Dec 2012
Event2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, TX, United Kingdom
Duration: 3 Oct 20125 Oct 2012

Conference

Conference2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
CountryUnited Kingdom
CityAustin, TX
Period3/10/125/10/12

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    Bolchini, C., Miele, A., Sandionigi, C., Ottavi, M., Pontarelli, S., Salsano, A., Metra, C., Omaña, M., Rossi, D., Reorda, M. S., Sterpone, L., Violante, M., Gerardin, S., Bagatin, M., & Paccagnella, A. (2012). High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 121-125). [6378211] https://doi.org/10.1109/DFT.2012.6378211