High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits. In particular, the reduced integration step, the reduced supply voltage that lowers the noise immunity, the growing power needs, the eventual integration of both digital and analog circuits on the same chip and the highly growing of radiation sensitivity [1], [2], [3] require an accurate evaluation of possible reliability reduction for the occurrence of: permanent faults due to the aging of device materials [4], the interruptions of metal interconnections due to electromigration [5] or the crack of the insulation oxide of transistor [6]; transient faults, known as Single Event Effects (SEE), which are much more likely than in the past due to the reduced transistors' sizes [3]: in particular new technology devices are more prone to crosstalk in the interconnects and to radiation effects.