High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer

Jiacheng Wang, Shunli Ma, P. D. Sai Manoj, Mingbin Yu, Roshan Weerasekera, Hao Yu

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

13 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	2013 IEEE International 3D Systems Integration Conference (3DIC)
Pages	1-4
Number of pages	4
DOIs	https://doi.org/10.1109/3DIC.2013.6702326
Publication status	Published - 2013

Research Groups and Themes

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title = "High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer",

author = "Jiacheng Wang and Shunli Ma and Manoj, \{P. D. Sai\} and Mingbin Yu and Roshan Weerasekera and Hao Yu",

year = "2013",

doi = "10.1109/3DIC.2013.6702326",

language = "Undefined/Unknown",

pages = "1--4",

booktitle = "2013 IEEE International 3D Systems Integration Conference (3DIC)",

}

TY - GEN

T1 - High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer

AU - Wang, Jiacheng

AU - Ma, Shunli

AU - Manoj, P. D. Sai

AU - Yu, Mingbin

AU - Weerasekera, Roshan

AU - Yu, Hao

PY - 2013

Y1 - 2013

U2 - 10.1109/3DIC.2013.6702326

DO - 10.1109/3DIC.2013.6702326

M3 - Conference Contribution (Conference Proceeding)

SP - 1

EP - 4

BT - 2013 IEEE International 3D Systems Integration Conference (3DIC)

ER -