High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

Thinh Hung Pham; Phong Tran; Siew-Kei Lam

doi:10.1109/TVLSI.2018.2881105

High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

Thinh Hung Pham, Phong Tran, Siew-Kei Lam

Department of Computer Science

Research output: Contribution to journal › Article (Academic Journal) › peer-review

18 Citations (Scopus)

Original language	English
Article number	8565982
Pages (from-to)	747-756
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	27
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2018.2881105
Publication status	Published - Apr 2019

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title = "High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction",

author = "Pham, {Thinh Hung} and Phong Tran and Siew-Kei Lam",

year = "2019",

month = apr,

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language = "English",

volume = "27",

pages = "747--756",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

number = "4",

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TY - JOUR

T1 - High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

AU - Pham, Thinh Hung

AU - Tran, Phong

AU - Lam, Siew-Kei

PY - 2019/4

Y1 - 2019/4

UR - https://doi.org/10.1109/TVLSI.2018.2881105

U2 - 10.1109/TVLSI.2018.2881105

DO - 10.1109/TVLSI.2018.2881105

M3 - Article (Academic Journal)

SN - 1063-8210

VL - 27

SP - 747

EP - 756

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 4

M1 - 8565982

ER -

High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

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