Impact of technology scaling on SRAM soft error rates

I. Chatterjee, B. Narasimham, N. N. Mahatme, B. L. Bhuva, R. A. Reed, R. D. Schrimpf, J. K. Wang, N. Vedula, B. Bartz, C. Monzel

Research output: Contribution to journalArticle (Academic Journal)

44 Citations (Scopus)

Abstract

Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual-and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

Original languageEnglish
Article number6957610
Pages (from-to)3512-3518
Number of pages7
JournalIEEE Transactions on Nuclear Science
Volume61
Issue number6
DOIs
Publication statusPublished - 1 Dec 2014

Keywords

  • Dual well
  • multiple-node charge collection
  • pulse quenching
  • reinforcing charge collection
  • scaling trends
  • single event upset reversal (SEUR)
  • soft error
  • static random access memories (SRAM)
  • triple-well

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