Abstract
Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made. © 2014 IEEE.
Original language | English |
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Title of host publication | IEEE International Reliability Physics Symposium Proceedings |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 5F.2.1 - 5F.2.6 |
ISBN (Print) | 9781479933167 |
DOIs | |
Publication status | Published - Jun 2014 |
Event | 52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United Kingdom Duration: 1 Jun 2014 → 5 Jun 2014 |
Conference
Conference | 52nd IEEE International Reliability Physics Symposium, IRPS 2014 |
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Country/Territory | United Kingdom |
City | Waikoloa, HI |
Period | 1/06/14 → 5/06/14 |
Keywords
- Combinational logic
- frequency
- technology scaling
- Technology scaling Soft errors