We introduce the Skip-link architecture that dynamically reconfigures Network- on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communi- cating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our archi- tecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reduc- tions of 12–17%. Coupled with this, we observe up to a doubling in critical load and the potential for 10% energy reductions on a 16 x 16 node network.
|Translated title of the contribution||Implementation and Evaluation of Skip-links: A Dynamically Reconfiguring Topology for Energy-efficient NoCs|
|Number of pages||29|
|Journal||International Journal of Embedded and Real-Time Communication Systems (IJERTCS)|
|Publication status||Published - Sep 2011|