Implementing the Draft RISC-V Scalar Cryptography Extensions

Ben Marshall, Daniel Page, Thinh H Pham

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)


RISC-V is an increasingly popular, free and open Instruction Set Ar-
chitecture (ISA). Many standard extensions to RISC-V are currently
being designed and evaluated, including one for accelerating cryp-
tographic workloads. Unlike most incumbent ISAs which re-use
existing large SIMD state and data-paths to accelerate cryptographic
operations, RISC-V also adds support for smaller machines with
narrow 32 and 64-bit data-paths. For embedded, IoT class devices,
this significantly lowers the barrier to entry for secure and effi-
cient accelerated cryptography. In this paper, we describe (to our
knowledge) the first complete, free and open-source implementa-
tion of the draft 32-bit RISC-V Cryptography Extension. We detail
the performance benefits for several important algorithms, and as-
sociated hardware costs. Our experiences help to guide the ongoing
standardisation work and provide a platform for other researchers
to experiment with a complete and representative CPU system,
implementing the draft cryptography extension.
Original languageEnglish
Title of host publicationHASP '20: Proceedings of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy
Publication statusPublished - 17 Nov 2020


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