Improved GaN-on-SiC transistor thermal resistance by systematic nucleation layer growth optimization

J. Pomeroy, N. Rorsman, Jr Tai Chen, U. Forsberg, E. Janzen, M. Kuball

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Abstract

Impressive power densities have been demonstrated for GaN-on-SiC based high-power high-frequency transistors, although further gains can be achieved by further minimizing the device thermal resistance. A significant 10-30% contribution to the total device thermal resistance originates from the high defect density AlN nucleation layer at the GaN/SiC interface. This thermal resistance contribution was successfully reduced by performing systematic growth optimization, investigating growth parameters including: Substrate pretreatment temperature, growth temperature and deposition time. Interfacial thermal resistance, characterized by time resolved Raman thermography measurements AlGaN/GaN HEMT structures, were minimized by using a substrate pretreatment and growth temperature of 1200 °C. Reducing the AlN thickness from 105 nm (3.3×10-8 W/m2K) to 35 nm (3.3×10-8 W/m2K), led to a ~2.5× interfacial thermal resistance reduction and the lowest value reported for a standard AlGaN/GaN HEMT structure.

Original languageEnglish
Title of host publicationTechnical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
DOIs
Publication statusPublished - 8 Nov 2013
Event2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Monterey, CA, United States
Duration: 13 Oct 201316 Oct 2013

Conference

Conference2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013
CountryUnited States
CityMonterey, CA
Period13/10/1316/10/13

Structured keywords

  • CDTR

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