Improvement of Electron Transport Property and On-Resistance in Normally-Off Al2O3/AlGaN/GaN MOS-HEMTs Using Post-Etch Surface Treatment

Jiejie Zhu, Siqi Jing, Xiaihua Ma, Siyu Liu, Penfei Wang, Yingcong Zhang, Qing Zeng Zhu, Minhan Mi, Ling Yang, Martin H H Kuball, Yue Hao

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Abstract

Post-etch surface treatment technique was developed for normally-off recess-gate Al2O3/AlGaN/GaN metal-oxide- semiconductor high-electron-mobility transistors (MOS-HEMTs). By removing the residues and smoothing surface morphology after plasma etch, the diffusion-controlled interface oxidation (DCIO) and wet etch in MOS-HEMTs leads to a decrease in interface traps from 1.04×1012 cm-2 to 6.3×1011 cm-2 with filling voltage of 12 V. Field-effect mobility extracted in the linear region is 48 cm2/Vs· for MOS-HEMTs with an optimized post-etch surface treatment process, 33% larger than the case with conventional chemical clean process. Due to the increased electron mobility and decreased sheet resistance beneath the gate by over 30%, normally-off MOS-HEMTs with DCIO and wet etch exhibit a remarkable increase in output current by about 29% and an increase in peak transconductance from 35 mS/mm to 41 mS/mm. The optimized post-etch surface treatment method also enhances blocking voltage from 120 V to 230 V, by suppressing the leakage current resulting from gate soft breakdown. Dynamic characterization shows that the normalized on-resistance is increased by double with drain stress up to 80 V, and various post-etch surface treatment process has little effect on current collapse. Two types of threshold voltage shifts caused by interface trapping and border trapping are observed in the normally-off MOS-HEMTs, which keeps stable with an increase in temperature up to 125 ℃.
Original languageEnglish
Pages (from-to)3541 - 3547
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume67
Issue number9
DOIs
Publication statusPublished - 20 Jul 2020

Structured keywords

  • CDTR

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