Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and production costs rise sharply. In this paper, a new approach for designing memory chips to be manufactured using future technologies is proposed, aiming to increase the overall yield. The proposed approach trades a small area overhead for dramatic production cost reduction, by allowing to use more defective memory chips as lower capacity ones, instead of discarding them.
|Translated title of the contribution||Increasing Memory Yield in Future Technologies through Innovative Design|
|Title of host publication||IEEE International Symposium on Quality Electronic Design. (ISQED 09)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Published - 2009|
Bibliographical noteOther page information: -
Conference Proceedings/Title of Journal: IEEE International Symposium on Quality Electronic Design. (ISQED 09)
Other identifier: 2000959