Initialisation and Synchronisation for a Dynamic Topology Network-On-Chip Architecture

CR Jackson, SJ Hollis

Research output: Other contribution

Abstract

Networks-on-Chip (NoCs) provide a Globally Asynchronous Locally Synchronous communication (GALS) fabric for VLSI. We propose a Network-on-Chip architecture that supports dynamic topology changes. These changes take the form of ‘bypass paths’ that allow routers to be traversed by flits without being buffered or switched. Each individual bypass uses an extra layer of topology switches to directly connect a router’s input link to its output link in the opposite direction. When the bypass paths are placed suitably an overall reduction in network router activity is achieved, reducing overall energy expenditure and latency. The architecture is supported by an adaptive deadlock-free routing algorithm that ensures routability. We present two solutions to mitigate potential local synchronisation problems when performing topology alterations: the first allows almost immediate changes and uses an arbiter to ensure flit ordering is maintained; the other introduces a delay but requires no extra logic. In addition, the algorithm that places bypass paths in the network is described
Translated title of the contributionInitialisation and Synchronisation for a Dynamic Topology Network-On-Chip Architecture
Original languageEnglish
TypeWorkshop Paper
Publication statusPublished - Sep 2009

Bibliographical note

Name and Venue of Event: 21st UK Async Forum

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