Inter and Intra-core Power Modelling for Single-ISA Heterogeneous Processors

Kris Nikov; Jose Nunez-Yanez

doi:10.1504/IJES.2020.10021023

Inter and Intra-core Power Modelling for Single-ISA Heterogeneous Processors

Kris Nikov, Jose Nunez-Yanez

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Abstract

This research presents a systematic methodology for producting accurate power models for single Instruction Set Architecture(ISA) heterogeneous processors. We use the hardware event counters from the processor Performance Monitoring Unit(PMU) to accurately capture the CPU states and Ordinary Least Squares(OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predications across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

Original language	English
Journal	International Journal of Embedded Systems
Volume	12
Issue number	3
Early online date	28 Apr 2020
DOIs	https://doi.org/10.1504/IJES.2020.10021023
Publication status	E-pub ahead of print - 28 Apr 2020

Keywords

big.LITTLE System-on-Chip
Linear Regression
Ordinary Least Squares
Hardware Performance Events
Automated Event Selection

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10.1504/IJES.2020.10021023

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This is the author accepted manuscript (AAM). The final published version (version of record) is available online via INDERSCIENCE Publishers at https://www.inderscience.com/info/inarticle.php?artid=107046 . Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 10.4 MB

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)
Nunez-Yanez, J. L.
5/01/16 → 4/01/20
Project: Research

Cite this

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title = "Inter and Intra-core Power Modelling for Single-ISA Heterogeneous Processors",

abstract = "This research presents a systematic methodology for producting accurate power models for single Instruction Set Architecture(ISA) heterogeneous processors. We use the hardware event counters from the processor Performance Monitoring Unit(PMU) to accurately capture the CPU states and Ordinary Least Squares(OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predications across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.",

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AU - Nikov, Kris

AU - Nunez-Yanez, Jose

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N2 - This research presents a systematic methodology for producting accurate power models for single Instruction Set Architecture(ISA) heterogeneous processors. We use the hardware event counters from the processor Performance Monitoring Unit(PMU) to accurately capture the CPU states and Ordinary Least Squares(OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predications across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

AB - This research presents a systematic methodology for producting accurate power models for single Instruction Set Architecture(ISA) heterogeneous processors. We use the hardware event counters from the processor Performance Monitoring Unit(PMU) to accurately capture the CPU states and Ordinary Least Squares(OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predications across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

KW - big.LITTLE System-on-Chip

KW - Linear Regression

KW - Ordinary Least Squares

KW - Hardware Performance Events

KW - Automated Event Selection

U2 - 10.1504/IJES.2020.10021023

DO - 10.1504/IJES.2020.10021023

M3 - Article (Academic Journal)

VL - 12

JO - International Journal of Embedded Systems

JF - International Journal of Embedded Systems

SN - 1741-1068

IS - 3

ER -

Inter and Intra-core Power Modelling for Single-ISA Heterogeneous Processors

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Keywords

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)

Cite this