Intra and inter-core power modelling for single-ISA heterogeneous processors

Krastin Nikov, Jose Nunez-Yanez*

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)peer-review

5 Citations (Scopus)
138 Downloads (Pure)


This research presents a systematic methodology for producing accurate power models for single instruction set architecture (ISA) heterogeneous processors. We use the hardware event counters from the processor performance monitoring unit (PMU) to accurately capture the CPU states and ordinary least squares (OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predictions across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

Original languageEnglish
Pages (from-to)324-340
Number of pages17
JournalInternational Journal of Embedded Systems
Issue number3
Early online date28 Apr 2020
Publication statusPublished - 2020

Bibliographical note

Funding Information:
This work is supported by ARM Research funding, through an EPSRC iCASE studentship and the University of Bristol and by the EPSRC ENEAC grant number EP/N002539/1.

Publisher Copyright:
Copyright © 2020 Inderscience Enterprises Ltd.


  • Automated event selection
  • Big.LITTLE system-on-chip
  • Energy efficiency
  • Energy prediction
  • Hardware performance events
  • Heterogenous processor
  • Linear regression
  • Ordinary least squares
  • Power modelling


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