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Inter and Intra-core Power Modelling for Single-ISA Heterogeneous Processors

Research output: Contribution to journalArticle

Original languageEnglish
JournalInternational Journal of Embedded Systems
DateAccepted/In press - 4 Feb 2019


This research presents a systematic methodology for producting accurate power models for single Instruction Set Architecture(ISA) heterogeneous processors. We use the hardware event counters from the processor Performance Monitoring Unit(PMU) to accurately capture the CPU states and Ordinary Least Squares(OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predications across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

    Research areas

  • big.LITTLE System-on-Chip, Linear Regression, Ordinary Least Squares, Hardware Performance Events, Automated Event Selection



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