Interface processor

David May (Inventor)

Research output: Patent

Abstract

The invention provides a processor comprising a first port operable to generate a first indication dependent on a first activity at the first port, and a second port operable to generate a second indication dependent on a second activity at the second port. The processor also comprises an execution unit arranged to execute multiple threads; and a thread scheduler connected to receive the indications and arranged to schedule the multiple threads for execution by the execution unit based on those indications. The scheduling includes suspending the execution of a thread until receipt of the respective ready signal. The first activity and the second activity are each associated with respective corresponding threads.
Original languageEnglish
Patent numberUS8219789
IPCG06F 9/00 9/30
Publication statusPublished - 10 Jul 2012

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