Investigation of a parasitic-inductance reduction technique for through-hole packaged power devices

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Abstract

Parasitic inductance in power electronic circuits can be problematic, giving rise to unwanted overshoots and ringing after switching transients. Whilst the aim is usually to minimize parasitic inductance, the use of through-hole packaged devices with relatively large insertion inductance may be unavoidable, for example due to heat dissipation requirements or device availability. This paper investigates the effectiveness of a technique for reducing the insertion inductance of through-hole packaged devices. The technique is demonstrated with a custom heatsink design for a TO220-packaged Schottky diode. The technique is to exploit the image-plane concept, bringing conductive layers as close as possible to the current loops within the device and its leads. Measurements in a switchmode GaN test circuit show that the heatsink reduces the parasitic inductance of the diode by 17% when compared to a conventional heatsink.
Original languageEnglish
Title of host publication2018 IEEE Energy Conversion Congress and Exposition (ECCE 2018)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1964-1968
Number of pages5
ISBN (Electronic)9781479973125
ISBN (Print)9781479973132
DOIs
Publication statusE-pub ahead of print - 6 Dec 2018

Publication series

Name
ISSN (Print)2329-3721

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Dymond, H., & Stark, B. H. (2018). Investigation of a parasitic-inductance reduction technique for through-hole packaged power devices. In 2018 IEEE Energy Conversion Congress and Exposition (ECCE 2018) (pp. 1964-1968). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ECCE.2018.8558152