Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6 inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). Acceleration models are discussed A measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined.
|Title of host publication||229th ECS Meeting May 29, 2016 - June 2, 2016 San Diego, CA|
|Subtitle of host publication||Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6|
|Editors||F Roozeboom, V Narayanan, K Kakushima, P J Timans, E P Gusev, Z Karim, S De Gendt|
|Publisher||The Electrochemical Society, Inc|
|Number of pages||12|
|Publication status||Published - 19 May 2016|