With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.
- Combinational logic mitigation
- kernel-based partition
- Low-power design