Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography

Sailong  Fan; Weiqiang Liu; James Howe; Ayesha Khalid; Maire O'Neill

doi:10.1109/APCCAS.2018.8605630

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography

Sailong Fan, Weiqiang Liu, James Howe, Ayesha Khalid, Maire O'Neill

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

18 Citations (Scopus)

368 Downloads (Pure)

Abstract

Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ring-learning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The R-LWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA show that the design consumes 808 slices and the frequency can be up to 288.35MHz.

Original language	English
Title of host publication	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	403-406
Number of pages	4
ISBN (Electronic)	9781538682401
DOIs	https://doi.org/10.1109/APCCAS.2018.8605630
Publication status	Published - 10 Jan 2019
Event	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China Duration: 26 Oct 2018 → 30 Oct 2018

Conference

Conference	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Country/Territory	China
City	Chengdu
Period	26/10/18 → 30/10/18

Keywords

cumulative distribution table
FPGA
lattice-based cryptography
polynomial multiplication
ring-learning with errors

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10.1109/APCCAS.2018.8605630

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This is the accepted author manuscript (AAM). The final published version (version of record) is available online via IEEE at https://doi.org/https://doi.org/10.1109/APCCAS.2018.8605630 . Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 1.18 MBLicence: Other

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title = "Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography",

abstract = "Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ring-learning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The R-LWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA show that the design consumes 808 slices and the frequency can be up to 288.35MHz.",

keywords = "cumulative distribution table, FPGA, lattice-based cryptography, polynomial multiplication, ring-learning with errors",

author = "Sailong Fan and Weiqiang Liu and James Howe and Ayesha Khalid and Maire O'Neill",

year = "2019",

month = jan,

day = "10",

doi = "10.1109/APCCAS.2018.8605630",

language = "English",

pages = "403--406",

booktitle = "2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 ; Conference date: 26-10-2018 Through 30-10-2018",

}

Fan, S, Liu, W, Howe, J, Khalid, A & O'Neill, M 2019, Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography. in 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018., 8605630, Institute of Electrical and Electronics Engineers (IEEE), pp. 403-406, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 26/10/18. https://doi.org/10.1109/APCCAS.2018.8605630

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography. / Fan, Sailong ; Liu, Weiqiang; Howe, James et al.
2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers (IEEE), 2019. p. 403-406 8605630.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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T1 - Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography

AU - Fan, Sailong

AU - Liu, Weiqiang

AU - Howe, James

AU - Khalid, Ayesha

AU - O'Neill, Maire

PY - 2019/1/10

Y1 - 2019/1/10

N2 - Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ring-learning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The R-LWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA show that the design consumes 808 slices and the frequency can be up to 288.35MHz.

AB - Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ring-learning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The R-LWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA show that the design consumes 808 slices and the frequency can be up to 288.35MHz.

KW - cumulative distribution table

KW - FPGA

KW - lattice-based cryptography

KW - polynomial multiplication

KW - ring-learning with errors

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M3 - Conference Contribution (Conference Proceeding)

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BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

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Y2 - 26 October 2018 through 30 October 2018

ER -

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography

Abstract

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Side channel aware software design flow

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Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography

Abstract

Conference

Keywords

Access to Document

Handle.net

Other files and links

Fingerprint

Projects

Side channel aware software design flow

Cite this