Logic insertion to speed-up logic verification: a recent development

D Pradhan

Logic insertion to speed-up logic verification: a recent development

D Pradhan

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

Logic verification continues to be considered one of CAD's most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This paper reviews certain current innovations addressing such problems. A new method is discussed, based on what has become known as the Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques - proven most powerful when traditional approaches, such as OBDD, fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits - discovering some bugs in the process

Translated title of the contribution	Logic insertion to speed-up logic verification: a recent development
Original language	English
Title of host publication	Unknown
Pages	61 - 64
Number of pages	3
Publication status	Published - Jul 2001

Bibliographical note

Conference Proceedings/Title of Journal: Seventh International On-Line Testing Workshop, 2001. Proceedings.

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@inproceedings{899fadb379a8459fb6646e0db87125f0,

title = "Logic insertion to speed-up logic verification: a recent development",

abstract = "Logic verification continues to be considered one of CAD's most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This paper reviews certain current innovations addressing such problems. A new method is discussed, based on what has become known as the Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques - proven most powerful when traditional approaches, such as OBDD, fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits - discovering some bugs in the process ",

author = "D Pradhan",

note = "Conference Proceedings/Title of Journal: Seventh International On-Line Testing Workshop, 2001. Proceedings. ",

year = "2001",

month = jul,

language = "English",

pages = "61 -- 64",

booktitle = "Unknown",

}

TY - GEN

T1 - Logic insertion to speed-up logic verification: a recent development

AU - Pradhan, D

N1 - Conference Proceedings/Title of Journal: Seventh International On-Line Testing Workshop, 2001. Proceedings.

PY - 2001/7

Y1 - 2001/7

N2 - Logic verification continues to be considered one of CAD's most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This paper reviews certain current innovations addressing such problems. A new method is discussed, based on what has become known as the Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques - proven most powerful when traditional approaches, such as OBDD, fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits - discovering some bugs in the process

AB - Logic verification continues to be considered one of CAD's most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This paper reviews certain current innovations addressing such problems. A new method is discussed, based on what has become known as the Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques - proven most powerful when traditional approaches, such as OBDD, fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits - discovering some bugs in the process

M3 - Conference Contribution (Conference Proceeding)

SP - 61

EP - 64

BT - Unknown

ER -

Logic insertion to speed-up logic verification: a recent development

Abstract

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