Logic insertion to speed-up logic verification: a recent development

D Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

Logic verification continues to be considered one of CAD's most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This paper reviews certain current innovations addressing such problems. A new method is discussed, based on what has become known as the Recursive Learning Technique. This proposed technique has its cornerstone in Boolean implication techniques - proven most powerful when traditional approaches, such as OBDD, fail. In fact, Recursive Learning was the first to verify the ISCAS benchmark circuits - discovering some bugs in the process
Translated title of the contributionLogic insertion to speed-up logic verification: a recent development
Original languageEnglish
Title of host publicationUnknown
Pages61 - 64
Number of pages3
Publication statusPublished - Jul 2001

Bibliographical note

Conference Proceedings/Title of Journal: Seventh International On-Line Testing Workshop, 2001. Proceedings.

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