Logic LOT: Logic Optimization with Testability--New Transformations for Logic Synthesis

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15 Citations (Scopus)

Translated title of the contribution	Logic LOT: Logic Optimization with Testability--New Transformations for Logic Synthesis
Original language	English
Pages (from-to)	386 - 399
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	17 (5)
Publication status	Published - 1998

Handle.net

@article{32f0b5022a6a40a297cfd459b92e5cf0,

title = "Logic LOT: Logic Optimization with Testability--New Transformations for Logic Synthesis",

author = "M Chatterjee and DK Pradhan and W Kunz",

year = "1998",

language = "English",

volume = "17 (5)",

pages = "386 -- 399",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

}

TY - JOUR

T1 - Logic LOT

T2 - Logic Optimization with Testability--New Transformations for Logic Synthesis

AU - Chatterjee, M

AU - Pradhan, DK

AU - Kunz, W

PY - 1998

Y1 - 1998

M3 - Article (Academic Journal)

SN - 0278-0070

VL - 17 (5)

SP - 386

EP - 399

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ER -