Logic Synthesis for Arithmetic Circuits using the Reed-Muller Representation

JM Saul

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Translated title of the contributionLogic Synthesis for Arithmetic Circuits using the Reed-Muller Representation
Original languageEnglish
Title of host publicationUnknown
Pages109 - 113
Number of pages4
Publication statusPublished - 1992

Bibliographical note

Conference Proceedings/Title of Journal: European Conf. on Design Automation, 16-19 March 1992
Other: # IEEE Computer Society Press

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