Logic Synthesis for Arithmetic Circuits using the Reed-Muller Representation

JM Saul

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Translated title of the contribution	Logic Synthesis for Arithmetic Circuits using the Reed-Muller Representation
Original language	English
Title of host publication	Unknown
Pages	109 - 113
Number of pages	4
Publication status	Published - 1992

Conference Proceedings/Title of Journal: European Conf. on Design Automation, 16-19 March 1992
Other: # IEEE Computer Society Press

Handle.net

@inproceedings{5d175d54e2624a34be74aa794bc23808,

title = "Logic Synthesis for Arithmetic Circuits using the Reed-Muller Representation",

author = "JM Saul",

note = "Conference Proceedings/Title of Journal: European Conf. on Design Automation, 16-19 March 1992 Other: \# IEEE Computer Society Press",

year = "1992",

language = "English",

isbn = "081866453",

pages = "109 -- 113",

booktitle = "Unknown",

}