Long-term positive and negative gate bias stress tests on parallel connected SiC MOSFETs at −40 °C and 175 °C

Bias temperature instability (BTI) is known to adversely impact the performance of parallel connected SiC MOSFETs. The short circuit robustness of SiC modules is known to reduce with increased threshold voltage (VTH) variation within the parallel devices due to poor current sharing. In this paper, 400-h positive BTI (VGS = 25 V) and negative BTI (VGS = −10 V) stress tests at both −40 °C and 175 °C have been performed on 5 parallel connected SiC MOSFETs. Both the individual VTH shift for each of the 5 devices and the module VTH shift have been measured alongside the VTH range (highest VTH minus lowest VTH). Bipolar preconditioning has been performed before VTH measurement to record both the peak VTH (measured before bipolar preconditioning) and permanent VTH (measured after bipolar preconditioning). The results show that p-BTI stress yields 21 % higher peak module VTH shift compared to n-BTI at −40 °C and 29 % higher at 175 °C. The measured VTH range was unchanged by the BTI tests if permanent VTH shift is assessed. However, the peak VTH range was higher after stressing thereby indicating increased variability in the injected temporary charge. The peak VTH range also exhibits a positive temperature coefficient indicating that temperature increases variability of the injected charge. If VTH range is taken as an indicator of short circuit robustness in parallel connected devices, the measurements presented show that bipolar preconditioning ensures that the short circuit performance of the module would likely be unaffected by the stress tests since ΔVTH shift is uniform.