This paper discusses the development of a Hiperlan/1 radio modem for the simultaneous transmission of video, voice and data in the home environment. In particular, the performance of the wireless modem has been optimised to support MPEG II video streams. The modem will eventually be integrated with digital set-top box equipment to support wireless Internet and digital television applications around the home. This paper describes a number of enhanced architectures and algorithms that enable an efficient FPGA implementation of the baseband digital equaliser, synchroniser and diversity combiner. Results show that the entire baseband receiver can easily fit within a single Xilinx Virtex device and that error-free packet rates in excess of 99% are possible, even in worst case radio channels.
|Translated title of the contribution||Low Complexity Synchronisation, Equalisation and Diversity Combining for Home-Based Hiperlan/1 Transceivers|
|Title of host publication||Proceedings of the 51st IEEE Vehicular Technology Conference, Tokyo, Japan|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||2242 - 2246|
|Publication status||Published - May 2000|
|Event||51st Vehicular Technology Conference 2000 (VTC 2000-Spring) - Tokyo, Japan|
Duration: 1 May 2000 → …
|Conference||51st Vehicular Technology Conference 2000 (VTC 2000-Spring)|
|Period||1/05/00 → …|
Bibliographical noteRose publication type: Conference contribution
Sponsorship: This study was performed as part of the ESPRIT WINHOME project (25048)
By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
- Hiperlan /I
- FPGA implementation