Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers

Y Sun, AR Nix, DJ Milford, DR Bull

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)
341 Downloads (Pure)

Abstract

This paper discusses the development of a Hiperlan/1 radio modem for the simultaneous transmission of video, voice and data in the home environment. In particular, the performance of the wireless modem has been optimised to support MPEG II video streams. The modem will eventually be integrated with digital set-top box equipment to support wireless Internet and digital television applications around the home. This paper describes a number of enhanced architectures and algorithms that enable an efficient FPGA implementation of the baseband digital equaliser, synchroniser and diversity combiner. Results show that the entire baseband receiver can easily fit within a single Xilinx Virtex device and that error-free packet rates in excess of 99% are possible, even in worst case radio channels.
Translated title of the contributionLow Complexity Synchronisation, Equalisation and Diversity Combining for Home-Based Hiperlan/1 Transceivers
Original languageEnglish
Title of host publicationProceedings of the 51st IEEE Vehicular Technology Conference, Tokyo, Japan
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages2242 - 2246
Volume3
ISBN (Print)0780357183
DOIs
Publication statusPublished - May 2000
Event51st Vehicular Technology Conference 2000 (VTC 2000-Spring) - Tokyo, Japan
Duration: 1 May 2000 → …

Conference

Conference51st Vehicular Technology Conference 2000 (VTC 2000-Spring)
CountryJapan
CityTokyo
Period1/05/00 → …

Bibliographical note

Rose publication type: Conference contribution

Sponsorship: This study was performed as part of the ESPRIT WINHOME project (25048)

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Keywords

  • Hiperlan /I
  • FPGA implementation

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