Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers

Y Sun; AR Nix; DJ Milford; DR Bull

doi:10.1109/VETECS.2000.851671

Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers

Y Sun, AR Nix, DJ Milford, DR Bull

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

1 Citation (Scopus)

432 Downloads (Pure)

Abstract

This paper discusses the development of a Hiperlan/1 radio modem for the simultaneous transmission of video, voice and data in the home environment. In particular, the performance of the wireless modem has been optimised to support MPEG II video streams. The modem will eventually be integrated with digital set-top box equipment to support wireless Internet and digital television applications around the home. This paper describes a number of enhanced architectures and algorithms that enable an efficient FPGA implementation of the baseband digital equaliser, synchroniser and diversity combiner. Results show that the entire baseband receiver can easily fit within a single Xilinx Virtex device and that error-free packet rates in excess of 99% are possible, even in worst case radio channels.

Translated title of the contribution	Low Complexity Synchronisation, Equalisation and Diversity Combining for Home-Based Hiperlan/1 Transceivers
Original language	English
Title of host publication	Proceedings of the 51st IEEE Vehicular Technology Conference, Tokyo, Japan
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	2242 - 2246
Volume	3
ISBN (Print)	0780357183
DOIs	https://doi.org/10.1109/VETECS.2000.851671
Publication status	Published - May 2000
Event	51st Vehicular Technology Conference 2000 (VTC 2000-Spring) - Tokyo, Japan Duration: 1 May 2000 → …

Conference

Conference	51st Vehicular Technology Conference 2000 (VTC 2000-Spring)
Country/Territory	Japan
City	Tokyo
Period	1/05/00 → …

Bibliographical note

Rose publication type: Conference contribution

Sponsorship: This study was performed as part of the ESPRIT WINHOME project (25048)

Terms of use: Copyright © 2000 IEEE. Reprinted from Proceedings of IEEE Vehicular Technology Conference, Spring 2000. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

Hiperlan /I
FPGA implementation

Access to Document

10.1109/VETECS.2000.851671

Sun IEEE VTC Spring 2000Accepted author manuscript, 617 KB

http://hdl.handle.net/1983/251

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Cite this

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title = "Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers",

abstract = "This paper discusses the development of a Hiperlan/1 radio modem for the simultaneous transmission of video, voice and data in the home environment. In particular, the performance of the wireless modem has been optimised to support MPEG II video streams. The modem will eventually be integrated with digital set-top box equipment to support wireless Internet and digital television applications around the home. This paper describes a number of enhanced architectures and algorithms that enable an efficient FPGA implementation of the baseband digital equaliser, synchroniser and diversity combiner. Results show that the entire baseband receiver can easily fit within a single Xilinx Virtex device and that error-free packet rates in excess of 99% are possible, even in worst case radio channels.",

keywords = "Hiperlan /I, FPGA implementation",

author = "Y Sun and AR Nix and DJ Milford and DR Bull",

note = "Rose publication type: Conference contribution Sponsorship: This study was performed as part of the ESPRIT WINHOME project (25048) Terms of use: Copyright {\textcopyright} 2000 IEEE. Reprinted from Proceedings of IEEE Vehicular Technology Conference, Spring 2000. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ; 51st Vehicular Technology Conference 2000 (VTC 2000-Spring) ; Conference date: 01-05-2000",

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Sun, Y, Nix, AR, Milford, DJ & Bull, DR 2000, Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers. in Proceedings of the 51st IEEE Vehicular Technology Conference, Tokyo, Japan. vol. 3, Institute of Electrical and Electronics Engineers (IEEE), pp. 2242 - 2246, 51st Vehicular Technology Conference 2000 (VTC 2000-Spring), Tokyo, Japan, 1/05/00. https://doi.org/10.1109/VETECS.2000.851671

Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers. / Sun, Y; Nix, AR; Milford, DJ et al.
Proceedings of the 51st IEEE Vehicular Technology Conference, Tokyo, Japan. Vol. 3 Institute of Electrical and Electronics Engineers (IEEE), 2000. p. 2242 - 2246.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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AB - This paper discusses the development of a Hiperlan/1 radio modem for the simultaneous transmission of video, voice and data in the home environment. In particular, the performance of the wireless modem has been optimised to support MPEG II video streams. The modem will eventually be integrated with digital set-top box equipment to support wireless Internet and digital television applications around the home. This paper describes a number of enhanced architectures and algorithms that enable an efficient FPGA implementation of the baseband digital equaliser, synchroniser and diversity combiner. Results show that the entire baseband receiver can easily fit within a single Xilinx Virtex device and that error-free packet rates in excess of 99% are possible, even in worst case radio channels.

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ER -

Low complexity synchronisation, equalisation and diversity combining for home-based Hiperlan/1 transceivers

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Keywords

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